1. Field
Example embodiments relate to a semiconductor device and a method of fabricating the same. Other example embodiments relate to a semiconductor device having a capacitor and a method of fabricating the same.
2. Description of the Related Art
Generally, a capacitor may be used in a semiconductor device because of its electrical charge storing function. A unit cell of a D-RAM may include a capacitor as an element to store electrical charges. Due to a relatively high-integration trend of a semiconductor device, an area for a capacitor has been gradually reduced. A capacitor having a relatively high electrostatic capacity in a limited area is being developed.
A cylindrical capacitor may be used to increase the electrostatic capacity in a limited area. In the cylindrical capacitor, a top electrode may cover inner and outer sides of a cylindrical bottom electrode. Because an overlapping area of the bottom and top electrodes is increased in a limited area, an electrostatic capacity of the cylindrical capacitor may be improved. A method of forming a cylindrical bottom electrode will be described in detail with reference to FIGS. 1A to 1C.
FIGS. 1A to 1C are diagrams illustrating a method of forming a conventional cylindrical bottom electrode. Referring to FIG. 1A, an interlayer oxide layer 2 may be formed on a semiconductor substrate 1. Contact plugs 3 may be formed to contact the semiconductor substrate I through the interlayer oxide layer 2. An etch stop layer 4 and a mold oxide layer 5 may be sequentially formed on an entire surface of the semiconductor substrate 1. The etch stop layer 4 may be formed of a silicon nitride layer having an etch selectivity with respect to the mold oxide layer 5. The mold oxide layer 5 may be patterned to expose the etch stop layer 4 on the contact plug 3. The exposed etch stop layer 4 may be anisotropically etched to form an electrode hole 6 exposing the contact plug 3.
Referring to FIG. 1B, a conductive layer may be formed on an entire surface of the semiconductor substrate 1, and then a sacrificial oxide layer may be formed on the conductive layer. The sacrificial oxide layer and the conductive layer may be planarized to expose the top of the mold oxide layer 5, and then to form a cylindrical bottom electrode 7 and sacrificial oxide pattern 8 in the electrode hole 6. Referring to FIG. 1C, the mold oxide layer 5 and the sacrificial oxide pattern 8 may be removed using a wet etching process to expose the inner and outer sidewalls in the bottom electrode 7.
According to the method of forming the conventional cylindrical bottom electrode, when forming the electrode hole 6, the etch stop layer 4 exposed by patterning the mold oxide layer 5 may be removed using an anisotropic etching process. During this process, various problems may occur. In the anisotropic etching process, ionic components of etching gas may be anisotropically moved by an electrical field to etch target materials. Because this anisotropic etching process also may include etching by a physical reaction, an etch selectivity between materials may be reduced. For example, the etch stop layer 4 formed of a silicon nitride layer may be anisotropically etched generally using a process gas (e.g., fluorocarbon-based gas, argon gas and/or oxygen gas). An etch selectivity of the etch stop layer 4 to the mold oxide layer 5 may be about 4:1.
As illustrated FIGS. 1A to 1C, due to this relatively low etch selectivity, a bowing effect may occur so that the top of the electrode hole 6 may be formed in a jar shape when the exposed etch stop layer 4 is anisotropically etched. An interval between the bottom electrodes 7 formed along the sidewall of the electrode hole 6 may be decreased so that top sidewalls between adjacent bottom electrodes 7 may be contacted. Defects of the semiconductor device may occur. If an interval between the top sidewalls is decreased by the bowing effect, stiction may increase by the surface tension of a water layer when the mold oxide layer 5 and the sacrificial pattern 8 may be removed by a wet etching process. Contact phenomena between adjacent bottom electrodes 7 may occur more frequently.
When semiconductor devices are more highly integrated, an aspect ratio of the electrode hole 6 may be relatively high. By anisotropic-etching of the electrode hole 6 with a relatively high aspect ratio and the exposed etch stop layer 4, a portion of the etch stop layer 4 in the sidewall of the electrode hole 6 may be formed at a slant. The bottom area of the electrode hole 6 may be decreased, and also the bottom area of the bottom electrode may be decreased. Because a support portion of the bottom electrode 7 is decreased, the bottom electrode 7 may be more slanted. Due to the decrease of the support portion, the stiction may become more considerable.